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PROFET(R) BTS 740 S2 Smart High-Side Power Switch Two Channels: 2 x 30m Current Sense
Product Summary
Operating Voltage Vbb(on) Active channels On-state Resistance RON Nominal load current IL(NOM) Current limitation IL(SCr) 5.0...34V two parallel 15m 8.5A 24A
Package
P-DSO-20-9
one 30m 5.5A 24A
General Description
* * N channel vertical power MOSFET with charge pump, ground referenced CMOS compatible input, diagnostic feedback and proportional load current sense monolithically integrated in Smart SIPMOS technology. Providing embedded protective functions
Applications
* * * * C compatible high-side power switch with diagnostic feedback for 12V and 24V grounded loads All types of resistive, inductive and capacitve loads Most suitable for loads with high inrush currents, so as lamps Replaces electromechanical relays, fuses and discrete circuits
Basic Functions
* * * * CMOS compatible input Undervoltage and overvoltage shutdown with auto-restart and hysteresis Fast demagnetization of inductive loads Logic ground independent from load ground
Protection Functions
* * * * * * * * Short circuit protection Overload protection Current limitation Thermal shutdown Overvoltage protection (including load dump) with external resistor Reverse battery protection with external resistor Loss of ground and loss of Vbb protection Electrostatic discharge protection (ESD)
Vbb
IN1 ST1 IS1 IN2 ST2 IS2
Logic Channel 1 Logic Channel 2 PROFET GND
OUT 1 Load 1 OUT 2 Load 2
Diagnostic Functions
* * * * Proportinal load current sense Diagnostic feedback with open drain output Open load detection in OFF-state with external resistor Feedback of thermal shutdown in ON-state
Semiconductor Group
1 of 15
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PROFET(R) BTS 740 S2
Functional diagram
overvoltage protection internal voltage supply logic
gate control + charge pump
current limit
VBB
clamp for inductive load OUT1
IN1
temperature sensor ESD Open load detection Current sense RO1 GND1 Channel 1 LOAD
ST1 IS1 GND1
IN2 ST2 IS2 GND2
Control and protection circuit of channel 2 OUT2
PROFET
Pin Definitions and Functions
Pin 1,10, 11,12, 15,16, 19,20 3 7 17,18 13,14 Symbol Function Vbb Positive power supply voltage. Design the wiring for the simultaneous max. short circuit currents from channel 1 to 2 and also for low thermal resistance IN1 Input 1,2, activates channel 1,2 in case of IN2 logic high signal OUT1 Output 1,2, protected high-side power output OUT2 of channel 1,2. Both pins of each output have to be connected in parallel for operation according ths spec (e.g. kilis). Design the wiring for the max. short circuit current ST1 Diagnostic feedback 1,2 of channel 1,2, ST2 open drain, invers to input level GND1 Ground 1 of chip 1 (channel 1) GND2 Ground 2 of chip 2 (channel 2) IS1 Sense current output 1,2; proportional to the load current, zero in the case of current IS2 limitation of the load current
Pin configuration
(top view)
4 8 2 6 5 9
Vbb GND1 IN1 ST1 IS1 GND2 IN2 ST2 IS2 Vbb
1 2 3 4 5 6 7 8 9 10
*
20 19 18 17 16 15 14 13 12 11
Vbb Vbb OUT1 OUT1 Vbb Vbb OUT2 OUT2 Vbb Vbb
Semiconductor Group
2
2003-Oct-01
PROFET(R) BTS 740 S2
Maximum Ratings at Tj = 25C unless otherwise specified
Parameter Supply voltage (overvoltage protection see page 5) Supply voltage for full short circuit protection Tj,start = -40 ...+150C Load current (Short-circuit current, see page 5) Load dump protection1) VLoadDump = VA + Vs, VA = 13.5 V RI2) = 2 , td = 200 ms; IN = low or high, each channel loaded with RL = 7.0 , Operating temperature range Storage temperature range Power dissipation (DC)4) Ta = 25C: (all channels active) Ta = 85C: Maximal switchable inductance, single pulse Vbb = 12V, Tj,start = 150C4), IL = 5.5 A, EAS = 370 mJ, 0 one channel: IL = 8.5 A, EAS = 790 mJ, 0 two parallel channels:
see diagrams on page 10
Symbol Vbb Vbb IL VLoad dump3) Tj Tstg Ptot
Values 43 34 self-limited 60 -40 ...+150 -55 ...+150 3.8 2.0
Unit V V A V C W
ZL
18 16 1.0 4.0 8.0 -10 ... +16 2.0 5.0 14
mH
Electrostatic discharge capability (ESD) IN: VESD (Human Body Model) ST, IS: out to all other pins shorted:
acc. MIL-STD883D, method 3015.7 and ESD assn. std. S5.1-1993 R=1.5k; C=100pF
kV
Input voltage (DC) Current through input pin (DC) Current through status pin (DC) Current through current sense pin (DC)
see internal circuit diagram page 9
VIN IIN IST IIS
V mA
Thermal Characteristics
Parameter and Conditions Symbol Values min typ Max ----40 33 12 --Unit
Thermal resistance junction - soldering point4),5) each channel: Rthjs 4) junction - ambient one channel active: Rthja all channels active:
K/W
1) 2) 3) 4) 5)
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 resistor for the GND connection is recommended. RI = internal resistance of the load dump test pulse generator VLoad dump is setup without the DUT connected to the generator per ISO 7637-1 and DIN 40839 Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70m thick) copper area for Vbb connection. PCB is vertical without blown air. See page 15 Soldering point: upper side of solder edge of device pin 15. See page 15
Semiconductor Group
3
2003-Oct-01
PROFET(R) BTS 740 S2
Electrical Characteristics
Parameter and Conditions, each of the two channels
at Tj = -40...+150C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max
Unit
Load Switching Capabilities and Characteristics On-state resistance (Vbb to OUT); IL = 5 A each channel, Tj = 25C: RON Tj = 150C: two parallel channels, Tj = 25C: Output voltage drop limitation at small load currents, see page 14
IL = 0.5 A Tj =-40...+150C:
--
27 54 14
30 60 15 ---
m
VON(NL)
-4.9 7.8 -25 25 0.1 0.1
50 5.5 8.5 -70 80 ---
mV A
Nominal load current
one channel active: IL(NOM) two parallel channels active:
Device on PCB6), Ta = 85C, Tj 150C
Output current while GND disconnected or pulled up7); IL(GNDhigh)
Vbb = 30 V, VIN = 0, see diagram page 10
8
150 200 1 1
mA
s
Turn-on time8) IN Turn-off time IN RL = 12 Slew rate on 8) 10 to 30% VOUT, RL = 12 : Slew rate off 8) 70 to 40% VOUT, RL = 12 :
Operating Parameters Operating voltage9) Undervoltage shutdown Undervoltage restart
to 90% VOUT: ton to 10% VOUT: toff
dV/dton -dV/dtoff
V/s V/s
Vbb(on) Vbb(under) Tj =-40...+25C: Vbb(u rst) Tj =+150C: Undervoltage restart of charge pump see diagram page 13 Tj =-40...+25C: Vbb(ucp) Tj =150C: Undervoltage hysteresis Vbb(under)
Vbb(under) = Vbb(u rst) - Vbb(under)
5.0 3.2 ----34 33
--4.5 4.7 -0.5 ---
34 5.0 5.5 6.0 6.5 7.0 -43 --
V V V V V V V
Overvoltage shutdown Overvoltage restart
6) 7) 8) 9)
Vbb(over) Vbb(o rst)
Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm2 (one layer, 70m thick) copper area for Vbb connection. PCB is vertical without blown air. See page 15 not subject to production test, specified by design See timing diagram on page 11. At supply voltage increase up to Vbb= 4.7 V typ without charge pump, VOUT Vbb - 2 V
Semiconductor Group
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PROFET(R) BTS 740 S2
Parameter and Conditions, each of the two channels
at Tj = -40...+150C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max -41 43 ---1 -47 8 24 ---52 30 50 20
Unit
Vbb(over) Tj =-40: Vbb(AZ) Ibb=40 mA Tj =+25...+150C: Standby current11) Tj =-40C...25C: Ibb(off) VIN = 0; Tj =150C: Leakage output current (included in Ibb(off)) IL(off) VIN = 0 Operating current 12), VIN = 5V, IGND = IGND1 + IGND2, one channel on: IGND two channels on: Overvoltage hysteresis Overvoltage protection10) Protection Functions13) Current limit, (see timing diagrams, page 12) Tj =-40C: IL(lim) Tj =25C: Tj =+150C: Repetitive short circuit current limit, Tj = Tjt each channel IL(SCr) two parallel channels
(see timing diagrams, page 12)
V V A A
---
1.2 2.4
3 6
mA
48 40 31 ----
56 50 37 24 24 2.0
65 58 45 ----
A
A
Initial short circuit shutdown time
Tj,start =25C: toff(SC)
ms
(see timing diagrams on page 12)
Output clamp (inductive load switch off)14) at VON(CL) = Vbb - VOUT, IL= 40 mA Tj =-40C: VON(CL) Tj =25C...150C: Thermal overload trip temperature Tjt Thermal hysteresis Tjt
41 43 150 --
-47 -10
-52 ---
V C K
10)
11) 12) 13
14)
Supply voltages higher than Vbb(AZ) require an external current limit for the GND and status pins (a 150 resistor in the GND connection is recommended). See also VON(CL) in table of protection functions and circuit diagram page 9. Measured with load; for the whole device; all channels off Add IST, if IST > 0 Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet. Fault conditions are considered as "outside" normal operating range. Protection functions are not designed for continuous repetitive operation. If channels are connected in parallel, output clamp is usually accomplished by the channel with the lowest VON(CL)
Semiconductor Group
5
2003-Oct-01
PROFET(R) BTS 740 S2
Parameter and Conditions, each of the two channels
at Tj = -40...+150C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max
Unit
Reverse Battery Reverse battery voltage 15) Drain-source diode voltage (Vout > Vbb) IL = - 4.0 A, Tj = +150C Diagnostic Characteristics Current sense ratio16), static on-condition,
VIS = 0...5 V, Vbb(on) = 6.517)...27V, Tj kILIS = IL / IIS
-Vbb -VON
---
-600
32 --
V mV
= -40C, IL = 5 A: kILIS Tj= -40C, IL= 0.5 A:
4350 3100 4350 3800
4800 4800 4800 4800 6.1 ----30 10 3 15
5800 7800 5350 6300 6.9 1 15 10 300 100 -4 40 V A
Tj= 25...+150C, IL= 5 A: Tj= 25...+150C, IL = 0.5 A: Current sense output voltage limitation
Tj = -40 ...+150C IIS = 0, IL = 5 A:
VIS(lim) IIS(LL) IIS(LH) IIS(SH) 18) tson(IS)
5.4 0 0 0 ---2 5
Current sense leakage/offset current Tj = -40 ...+150C VIN=0, VIS = 0, IL = 0: VIN=5 V, VIS = 0, IL = 0: VIN=5 V, VIS = 0, VOUT = 0 (short circuit) Current sense settling time to IIS static10% after positive input slope18), IL = 0 5A
s s s V k
Current sense settling time to 10% of IIS static after 0A negative input slope18), IL = 5 tsoff(IS) Current sense rise time (60% to 90%) after change 5A of load current18) IL = 2.5 tslc(IS) Open load detection voltage19) (off-condition) Internal output pull down (pin 17,18 to 2 resp. 13,14 to 6), VOUT=5 V VOUT(OL) RO
15)
16)
17) 18) 19)
Requires a 150 resistor in GND connection. The reverse load current through the intrinsic drain-source diode has to be limited by the connected load. Power dissipation is higher compared to normal operating conditions due to the voltage drop across the drain-source diode. The temperature protection is not active during reverse current operation! Input and Status currents have to be limited (see max. ratings page 3 and circuit page 9). This range for the current sense ratio refers to all devices. The accuracy of the kILIS can be raised at least by a factor of two by matching the value of kILIS for every single device. In the case of current limitation the sense current IIS is zero and the diagnostic feedback potential VST is High. See figure 2c, page 12. Valid if Vbb(u rst) was exceeded before. not subject to production test, specified by design External pull up resistor required for open load detection in off state.
Semiconductor Group
6
2003-Oct-01
PROFET(R) BTS 740 S2
Parameter and Conditions, each of the two channels
at Tj = -40...+150C, Vbb = 12 V unless otherwise specified
Symbol
Values min typ max
Unit
Input and Status Feedback20) Input resistance
(see circuit page 9)
RI VIN(T+) VIN(T-) VIN(T) IIN(off) IIN(on) td(ST OL3)
3.0 -1.5 -1 20 --
4.5 --0.5 -50 400
7.0 3.5 --50 90 --
k V V V A A s s s V
Input turn-on threshold voltage Input turn-off threshold voltage Input threshold hysteresis Off state input current VIN = 0.4 V: On state input current VIN = 5 V: Delay time for status with open load after Input neg. slope (see diagram page 13) Status delay after positive input slope
(not subject to production test, specified by design)
tdon(ST) tdoff(ST)
--5.4 ----
13 1 6.1 ----
--6.9 0.4 0.7 2
Status delay after negative input slope
(not subject to production test, specified by design)
Status output (open drain) Zener limit voltage Tj =-40...+150C, IST = +1.6 mA: VST(high) ST low voltage Tj =-40...+25C, IST = +1.6 mA: VST(low) Tj = +150C, IST = +1.6 mA: Status leakage current, VST = 5 V, Tj=25 ... +150C: IST(high)
A
20)
If ground resistors RGND are used, add the voltage drop across these resistors.
Semiconductor Group
7
2003-Oct-01
PROFET(R) BTS 740 S2
Truth Table
Input 1 Input 2 level Normal operation Currentlimitation Short circuit to GND Overtemperature Short circuit to Vbb Open load Undervoltage Overvoltage L H L H L H L H L H L H L H L H L Output 1 Output 2 level L H L H L L21) L L H H L24) H L L L L L Status 1 Status 2 level H L H H H H H H L22) L H (L25)) L H L H L H Current Sense 1 Current Sense 2 IIS 0 nominal 0 0 0 0 0 0 0 Negative output voltage clamp L = "Low" Level X = don't care Z = high impedance, potential depends on external circuit H = "High" Level Status signal after the time delay shown in the diagrams (see fig 5. page 13) Parallel switching of channel 1 and 2 is possible by connecting the inputs and outputs in parallel. The status outputs ST1 and ST2 have to be configured as a 'Wired OR' function with a single pull-up resistor. The current sense outputs IS1 and IS2 have to be connected with a single pull-down resistor.
Terms
V
Ibb
bb
I IN1
I ST1
Leadframe 3 IN1
ST1 Vbb
VON1 OUT1
17,18
I L1
I IN2
I ST2
Leadframe 7 IN2
ST2 Vbb
VON2 OUT2
13,14
I L2
V V IN1 ST1 IS1 VIS1 5
4 I IS1
PROFET Chip 1 GND1
2 IGND1
VOUT1
V V IN2 ST2 IS2 V IS2 9
8 I IS2
PROFET Chip 2 GND2
6 IGND2
VOUT2
R GND1
RGND2
Leadframe (Vbb) is connected to pin 1,10,11,12,15,16,19,20 External RGND optional; two resistors RGND1, RGND2 = 150 or a single resistor RGND = 75 for reverse battery protection up to the max. operating voltage.
21) 22) 23) 24) 25)
The voltage drop over the power transistor is Vbb-VOUT > 3V typ. Under this condition the sense current IIS is zero An external short of output to Vbb, in the off state, causes an internal current from output to ground. If RGND is used, an offset voltage at the GND and ST pins will occur and the VST low signal may be errorious. Low ohmic short to Vbb may reduce the output current IL and therefore also the sense current IIS. Power Transistor off, high impedance with external resistor between VBB and OUT
Semiconductor Group
8
2003-Oct-01
PROFET(R) BTS 740 S2
Input circuit (ESD protection), IN1 or IN2
R IN I
Inductive and overvoltage output clamp,
OUT1 or OUT2
+Vbb VZ
ESD-ZD I GND
I
I
V
ON
OUT
The use of ESD zener diodes as voltage clamp at DC conditions is not recommended.
Status output, ST1 or ST2
+5V
Power GND
VON clamped to VON(CL) = 47 V typ.
R ST(ON)
ST
Overvoltage and reverse batt. protection
+ 5V + Vbb V IN ST
GND
ESDZD
R ST RI Logic
Z2
ESD-Zener diode: 6.1 V typ., max 5.0 mA; RST(ON) < 375 at 1.6 mA. The use of ESD zener diodes as voltage clamp at DC conditions is not recommended.
RV R IS
IS
OUT
V
PROFET
Z1 GND
Current sense output
V IS I IS ESD-ZD GND R IS IS
R GND
Signal GND
R Load
Load GND
VZ1 = 6.1 V typ., VZ2 = 47 V typ., RGND = 150 , RST=15k, RI=4.5k typ., RIS=1k, RV=15k, In case of reverse battery the current has to be limited by the load. Temperature protection is not active
Open-load detection OUT1 or OUT2
ESD-Zener diode: 6.1 V typ., max 14 mA; RIS = 1 k nominal OFF-state diagnostic condition: VOUT > 3 V typ.; IN low
V bb
R
EXT
OFF Out ST Logic
V OUT
R
O
Signal GND
Semiconductor Group
9
2003-Oct-01
PROFET(R) BTS 740 S2
GND disconnect
Inductive load switch-off energy dissipation
E bb
IN
Vbb PROFET OUT
IN Vbb PROFET OUT
E AS
ELoad
ST GND V bb V IN V ST V GND
=
ST GND
ZL
{
R L
L
EL
ER
Any kind of load. In case of IN = high is VOUT VIN - VIN(T+). Due to VGND > 0, no VST = low signal available.
Energy stored in load inductance: EL = 1/2*L*I L While demagnetizing load inductance, the energy dissipated in PROFET is
2
GND disconnect with GND pull up
IN
Vbb PROFET OUT
EAS= Ebb + EL - ER= VON(CL)*iL(t) dt, with an approximate solution for RL > 0 : EAS= IL* L (V + |VOUT(CL)|) 2*RL bb
IL*RL
ST GND
ln (1+ |V
OUT(CL)|
)
V
V
bb
V IN ST
V
GND
Maximum allowable load inductance for a single switch off (one channel)4)
L = f (IL ); Tj,start = 150C, Vbb = 12 V, RL = 0 ZL [mH]
1000
Any kind of load. If VGND > VIN - VIN(T+) device stays off Due to VGND > 0, no VST = low signal available.
Vbb disconnect with energized inductive load
high
IN
Vbb
100
PROFET ST GND OUT
V
bb
10
For inductive load currents up to the limits defined by ZL (max. ratings and diagram on page 10) each switch is protected against loss of Vbb. Consider at your PCB layout that in the case of Vbb disconnection with energized inductive load all the load current flows through the GND connection.
1 2 3 4 5 6 7 8 9 10 11 12
IL [A]
Semiconductor Group
10
2003-Oct-01
PROFET(R) BTS 740 S2
Timing diagrams
Both channels are symmetric and consequently the diagrams are valid for channel 1 and channel 2
Figure 1a: Switching a resistive load, change of load current in on-condition:
IN
Figure 2a: Switching a resistive load, turn-on/off time and slew rate definition:
IN
t don(ST)
ST
t doff(ST)
VOUT
90% t on dV/dton 10% t dV/dtoff
VOUT t on t off t slc(IS) t slc(IS)
IL
off
Load 1 IIS t son(IS)
Load 2
IL
t
t soff(IS)
t
The sense signal is not valid during settling time after turn or change of load current.
Figure 1b: Vbb turn on: IN1
Figure 2b: Switching a lamp:
IN
IN2 V bb V
ST
OUT1
V
OUT
V
OUT2
ST1 open drain
I
L
ST2 open drain
t
t
proper turn on under all conditions
Semiconductor Group
11
2003-Oct-01
PROFET(R) BTS 740 S2
Figure 2c: Switching a lamp with current limit: Figure 3a: Turn on into short circuit: shut down by overtemperature, restart by cooling
IN1 other channel: normal operation
IN
ST
I
L1
I
V OUT
L(lim) I L(SCr)
IL
off(SC) IS 1 = 0
t
IIS t
ST 1 t
Heating up of the chip may require several milliseconds, depending on external conditions
Figure 2d: Switching an inductive load
IN
Figure 3b: Turn on into short circuit: shut down by overtemperature, restart by cooling (two parallel switched channels 1 and 2)
IN1/2
ST
I
L1
+I
L2
V
2xIL(lim)
OUT
I
L(SCr)
I
L
I L(OL) t
*) if the time constant of load is too large, open-load-status may occur
t
off(SC)
S 1= IS 2 = 0
ST 1/2 t
ST1 and ST2 have to be configured as a 'Wired OR' function ST1/2 with a single pull-up resistor.
Semiconductor Group
12
2003-Oct-01
PROFET(R) BTS 740 S2
Figure 4a: Overtemperature: Reset if Tj IN
Figure 6a: Undervoltage:
IN
ST IL
ST
not defined
V bb V
bb(under)
Vbb(u cp) Vbb(u rst)
I IS
I
L
TJ
IIS
t
t
Figure 6b: Undervoltage restart of charge pump
Figure 5a: Open load: detection (with REXT), turn on/off to open load
Von
VON(CL)
IN td(ST OL3) ST
VOUT
offstate
on-state
V
bb(over)
offstate
V
I L open load
bb(u rst)
V
bb(o rst)
V V
bb(under)
bb(u cp)
I IS
t
charge pump starts at Vbb(ucp) =4.7 V typ.
V bb
Semiconductor Group
13
2003-Oct-01
PROFET(R) BTS 740 S2
Figure 7a: Overvoltage:
Figure 8b: Current sense ratio:
15000 k ILIS
IN ST
10000
Vbb V ON(CL) V
bb(over)
V
bb(o rst)
IL
5000
I
IS t
0
[A] I L 0 1 2 3 4 5 6 7 8 9 10 11 12 13
Figure 8a: Current sense versus load current26::
1.3 [mA] 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 3 4 IL 5 [A] 6
Figure 9a: Output voltage drop versus load current:
VON
I IS
[V]
0.2 RON
0.1
VON(NL) IL 0 1 2 3 4 5 6 7 [A] 8
0.0
26
This range for the current sense ratio refers to all devices. The accuracy of the kILIS can be raised at least by a factor of two by matching the value of kILIS for every single device.
Semiconductor Group
14
2003-Oct-01
PROFET(R) BTS 740 S2 Package and Ordering Code
Standard: P-DSO-20-9
Sales Code Ordering Code
All dimensions in millimetres
BTS 740 L2 Q67060-S7012-A2
St.-Martin-Strasse 53, D-81669 Munchen (c) Infineon Technologies AG 2001 All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.
Definition of soldering point with temperature Ts: upper side of solder edge of device pin 15.
Pin 15
Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Printed circuit board (FR4, 1.5mm thick, one layer 70m, 6cm2 active heatsink area) as a reference for max. power dissipation Ptot, nominal load current IL(NOM) and thermal resistance Rthja
Semiconductor Group
15
2003-Oct-01

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